1. Field of the Invention
The present invention relates to an amplifier and more particularly, a sense amplifier for a memory device.
2. Background of the Related Art
One of the important factors in the semiconductor field is to operate a device at a high speed. One of the ways to increase the operating speed is to decrease the voltage level of a signal. Since a signal of low voltage level has a small swinging width, the transition of a logic state is fast. Although the voltage level of a signal is lowered to obtain a fast operation speed, the signal needs to be amplified eventually to a magnitude large enough to drive a load, especially when the signal is transferred through a very long signal line. In other words, the voltage level has to be amplified sufficiently.
FIG. 1 shows a schematic of a data output path for semiconductor memory according to a related art. Bit line sense amplifier circuits 104 and 108 of a DRAM in FIG. 1 amplify a minute voltage difference between each bit line pair BL and /BL connected to memory cell arrays 102 and 106 to data buses DB and /DB. Signals of the data buses DB and /DB are amplified by data bus sense amplifier circuits 110 and 112 and transferred to read data lines RDL and /RDL. The signals of the read data lines are carried to a data output pad through a read data driver and a data output buffer.
As memory capacity increases, so does the area of a memory cell array also increases. Thus, the length of the bit lines or data buses becomes longer. Accordingly, when an output of a bit line sense amplifier is connected directly to a read data line RDL or /RDL, it is hard to expect a fast amplifying operation from the sense amplifier due to the large load on the bit line sense amplifier. Instead, the load on the bit line is alleviated by amplifying the signal which has been amplified by the bit line sense amplifier with a data bus sense amplifier located on the data bus.
The bit line sense amplifier circuit 104 and 108 include a plurality of bit line sense amplifiers, each sense amplifier for a pair of bit lines BL and /BL. The data bus sense amplifier circuit 110 and 112 includes a plurality of sense amplifiers each for a pair of data buses DB and /DB.
FIG. 2 shows a circuit of a current mirror typed sense amplifier used for a semiconductor integrated circuit in a related art. Referring to FIG. 2, two PMOS transistors 202 and 204 connected to a power supply voltage VDD are an example of a current mirror typed load 200. Both gates of the PMOS transistors 202 and 204 are connected to a drain of the PMOS transistor 202.
Two NMOS transistors 206 and 208, serving as driving transistors, are connected to the PMOS transistors 202 and 204, respectively. The NMOS transistor 206 is driven by a data bus signal DB and the NMOS transistor 208 is driven by a data bus bar signal /DB which is a complementary signal of the data bus signal DB. Both of the NMOS transistors 206 and 208 are connected to a current source formed by NMOS transistor 210, which is activated by a sense amplifier enabling signal SAE.
Each current passing by nodes 212 and 214 is equal to each other because of the current mirror typed load 200. Thus, the current sinking through the NMOS transistor 210 of the current source to a ground VSS is constant. The current passing through the NMOS transistors 206 and 208 depends on voltage levels of the data bus signal DB and the data bus bar signal /DB, respectively.
When the voltage level of the data bus signal DB is higher than that of the data bus bar signal /DB (even though the difference is very small), drain-source current IDS of the NMOS transistor 206 increases relatively to lower the voltage at the node 212. On the other hand, drain-source current IDS of the NMOS transistor 208 decreases while voltage of the node 214 rises. Accordingly, the voltage difference between a pair of the data bus signals DB and /DB is amplified to a level of the power source voltage VDD.
FIG. 3 shows a circuit of a sense amplifier including two differential amplifiers connected in parallel to generate complementary outputs. A data bus signal DB and a data bar signal /DB are cross-coupled to both a first differential amplifier 420 and a second differential amplifier 422. The differential amplifiers 420 and 422 produce complementary outputs OUT and /OUT. In the first differential amplifier 420, a driving NMOS transistor 406 is driven by the data bus signal DB, and a first output OUT is generated from a drain thereof. The other driving NMOS transistor 408 is driven by the data bus bar signal /DB.
In the second differential amplifier 422, a driving NMOS transistor 418 is driven by the data bus bar signal /DB, and a second output /OUT, which is complementary to the first output OUT, is generated from a drain thereof. The other driving NMOS transistor 416 is driven by the data bus signal DB. The two differential amplifiers are for a single sense amplifier, which provides complementary outputs OUT and /OUT based on complementary data bias signal DB and data bus bar signal /DB.
FIG. 4 shows a circuit of a cross-coupled differential amplifier in a semiconductor integrated circuit which is generally used in a related art as a sense amplifier in semiconductor memory. Referring to FIG. 4, two PMOS transistors 602 and 604 are connected to a power supply voltage VDD in parallel and are cross-coupled type loads. Gates of the PMOS transistors 602 and 604 are connected to the drains of reciprocal PMOS transistors 604 and 602, respectively.
These two PMOS transistors 602 and 604, as the load, are connected to NMOS transistors 606 and 608 as driving transistors, respectively. The driving NMOS transistor 606 is driven by a data bus signal DB and the driving NMOS transistor 608 is driven by a data bus bar signal /DB. Both of the NMOS transistors 606 are connected to another NMOS transistor 610 which is a current source. The NMOS transistor 610, which serves as a current source, is activated by a sense amplifier enabling signal SAE.
When the sense amplifier enabling signal SAE is activated to high level, drain-source current IDS of the NMOS transistor 606 is larger than the other drain-source current IDS of the other NMOS transistor 608. Therefore, the voltage level of the data bus signal DB which drives the NMOS transistor 606 is higher than the voltage level of the data bus bar signal /DB of the NMOS transistor 608 to the height of the minute voltage difference xcex94V, which is very short. Accordingly, the voltage level of the second output /OUT is lower than the voltage level of the first output OUT.
The voltage of the first output OUT rises until a gate-source voltage VGS of the PMOS transistor 602 becomes greater than VDD+VTP (a threshold voltage). Then, the PMOS transistor 602 is turned off. Accordingly, the second output /OUT drops down to 0 volt VSS. Once the voltage of the second output /OUT falls down to 0 volt, and the gate-source voltage VGS drops under VDD+VTP. Thus, the first output OUT rises up to VDD.
In accordance with such amplification, the minute voltage difference xcex94V between the data bus signal DB and the data bus bar signal /DB are amplified to the level of the power supply voltage VDD.
It is the present trend in semiconductor memory to use a lower power supply voltage of 3.3V instead of 5V. Thus, the voltage level of a data bus signal is lower to be closer to the power supply voltage of 3.3V. Accordingly, a sense amplifier using a related current mirror typed differential amplifier is unable to provide a sufficient gain, and its operation speed is unfortunately decreased. In order to make up for these deficiencies, a level shifting is required by which an input voltage level of the differential amplifier is lowered to VDD/2 for maximizing the gain. A level shifter is discussed below for providing amplification at high speed using positive feed-back.
FIG. 5 shows a circuit of a sense amplifier including a level shifter 828 and a current mirror type differential amplifier 830. The level shifter 828 includes driving NMOS transistors 802 and 804, a first load 822 and a current source 810. The driving NMOS transistor 802 is driven by a data bus signal DB, and the driving NMOS transistor 804 is driven by a data bus bar signal /DB. The driving NMOS transistors 802 and 804 control voltage to limit a first internal output node 832 or a second internal output node 834 to a level of VDD/2, and have a relatively high threshold voltage VTN.
The first load 822, in which actual amplification is carried out, includes two load NMOS transistors 806 and 808. When the sense amplifier enabling signal SAE is activated, a drain-source current IDS of the driving NMOS transistor 802 is larger than the drain-source current IDS of the driving NMOS transistor 804. Therefore, the voltage level of the data bus signal DB which drives the driving NMOS transistor 802 is a voltage difference xcex94V higher than that of the data bus bar signal /DB of the driving NMOS transistor 804. Accordingly, the voltage at the first internal output node 832 is relatively higher than the voltage at the second internal output node 834.
The voltage of the first internal output node 832 rises until the threshold voltage of the NMOS transistor 808 exceeds VTN. Then, the NMOS transistor 808 is turned off. Accordingly, voltage of the second internal output node 834 drops down to 0 volt. Once the voltage of the second internal output node 834 drops to 0 volt, the NMOS transistor 806 is turned off. Thus, the voltage of the first internal output node 832 rises up to VDD/2. Namely, the small voltage difference xcex94V between the data bus signal DB and the data bus bar signal /DB is amplified up to VDD/2. The voltage difference xcex94V becomes the voltage difference between a first internal output OUTxe2x80x3 and a second internal output /OUTxe2x80x3.
The current mirror type differential amplifier 830 amplifies the first internal output OUTxe2x80x3 and the second internal output /OUTxe2x80x3 outputted from the level shifter 828. Gates of the load PMOS transistors 812 and 814 are connected to a drain of the load PMOS transistor 812.
Two driving NMOS transistors 816 and 818 connected to the load PMOS transistors 812 and 814, respectively. The NMOS transistor 816 is driven by the first internal output OUTxe2x80x3, and the NMOS transistor 818 is driven by the second internal output /OUTxe2x80x3. The driving NMOS transistors 816 and 818 are connected to the NMOS transistor 820, which operates as the current source and is activated by a sense amplifier enabling signal SAE. Each current passing through two nodes 836 and 838 is equal to each other because of the current mirror type load 826. Thus, the current sinking through the NMOS transistor 820 to a ground VSS remains constant.
Each current passing through the driving NMOS transistors 816 and 818 depends on voltage levels of the first and second internal outputs OUTxe2x80x3 and /OUTxe2x80x3, respectively. When the voltage level of the first internal output OUTxe2x80x3 is higher than the voltage level of the second internal output /OUTxe2x80x3, the drain-source current IDS of the driving NMOS transistor 816 increases relatively to lower the voltage at the node 836.
On the other hand, drain-source current IDS of the driving NMOS transistor 818 lessens relatively, while voltage at the node 838 rises. Accordingly, small voltage differences between the first and second internal outputs OUTxe2x80x3 and /OUTxe2x80x3 are amplified to a level of the power source voltage VDD.
As mentioned in the above description, the technology for increasing the integrity of a semiconductor chip has been developed successfully to support a large number of memory cells in a chip. Thus, the number of the bit line sense amplifiers and the data bus sense amplifiers is large.
Accordingly, in order to maximize the benefit of the increased number of memory cells integrated on a unit area, the area occupied by the unit bit line sense amplifier and the data bus sense amplifier should decrease. The integrity of a memory cell array increases remarkably by decreasing the area of the sense amplifiers since the area greatly affects a pitch of the memory cell.
An object of the present invention is to substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to reduce the size of the sense amplifiers.
Still another object is to have a common load for at least two sense amplifiers.
A further object of the present invention is to improve sense amplifier based on a current-mirror typed differential amplifier or a cross-coupled differential amplifier.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention for generating an amplified signal includes a load for coupling to a first voltage potential, a first driver circuit coupled to the load and controlled by a first data signal, and a second driver coupled to the load and controlled by a second data signal. The first and second drivers are commonly coupled to the load and the amplified signal of the first or second data signal is generated.
In another aspect of this embodiment, the load is a current mirror type and the amplified signal is a single output. In yet another aspect of this embodiment, the load is cross-coupled and the output is a signal which represents a logic value and a complement of the logic value. In still another aspect of this embodiment, the first driver has a first current source controlled by a first control signal and the second driver has a second current source controlled by a second control signal. In yet still another aspect of this embodiment, the first control signal is activated by a generation of the first data signal and the second control signal is activated by a generation of the second data signal.
In a further aspect of this embodiment, the first and second control signals are generated by an address transition detection signal. In yet a further aspect of this embodiment, a length of a signal line between the first driver and the first current source is equal to a length of another signal line between the second driver and the second current source. In still a further aspect of this embodiment, in the first current source, drains of first and second MOS transistors are connected to the first driver, a drain and source of a third MOS transistor are connected to the drain of the first MOS transistor and the drain of the second MOS transistor, respectively, and the first, second and third transistors are controlled by the first control signal, and in the second current source, drains of fourth and fifth MOS transistors are connected to the second driver, a drain and source of a sixth MOS transistor are connected to the drain of the fourth MOS transistor and the drain of the fifth MOS transistor, respectively, and the fourth, fifth and sixth transistors are controlled by the second control signal. In yet still a further aspect of this embodiment, the first driver includes at least one first driver unit and the second driver includes at least one second driver unit.
In another embodiment, the present invention includes a first load, a second load, a first amplifier, and a second amplifier. The first amplifier further includes a first driver supplied with a first data signal, and a second driver supplied with a second data signal. A first or second output which is an amplified signal of the first data signal is generated by having the first and second drivers own or be commonly connected to the second load. The second amplifier further includes a third driver controlled by the first data signal, and a fourth driver controlled by the second data signal. A first or second output which is an amplified signal of the second data signal is generated by having the third and fourth drivers commonly connected to the second load.
In a further embodiment, the present invention includes a level shifter, and an amplifier. The level shifter further includes a first load, a first driver controlled by a first data signal, and a second driver controlled by a second data signal. The first and second driver own the first load in common, and a first output is generated by changing a signal level of the first or second data signal. The amplifying means further includes a second load, and a third driver controlled by the first output. A second output is generated by amplifying a signal level of the first output.
The present invention can be achieved in a whole or in parts by an amplifier including a load for coupling to a first voltage potential, a first sense amplifier responsive to a first data signal, and a second sense amplifier responsive to a second data signal. The first and second sense amplifiers are commonly coupled to the load.
The present invention can also be achieved in a whole or in parts by an amplifier including a level shifter and an amplifying unit. The level shift includes: a first driver unit for limiting the level of a first voltage potential, a first load coupled to the first driver for amplifying a voltage difference, a first current source coupled to the first load and enabled by a first control signal, and a second current source coupled to the first load and enabled by a second control signal. The amplifying unit includes a second load for coupling to the first voltage potential, and a sense amplifier responsive to an output of the level shifter.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.